Comparator, circuit device, physical quantity sensor, electronic device, and vehicle

ABSTRACT

A comparator includes a first voltage-time conversion circuit, a second voltage-time conversion circuit, and a determination circuit. A first delay unit includes a first falling edge delay circuit that delays a falling edge based on a first input signal, a first rising edge delay circuit that delays a rising edge based on a second input signal, and a first output circuit. A second delay unit includes a second falling edge delay circuit that delays a falling edge based on the second input signal, a second rising edge delay circuit that delays a rising edge based on the first input signal, and a second output circuit.

BACKGROUND 1. Technical Field

The present invention relates to a comparator, a circuit device, a physical quantity sensor, an electronic device, a vehicle, or the like.

2. Related Art

A known time-domain type comparator converts an input voltage level into a time (for example, a delay time of a signal edge, a pulse width of a pulse signal, a period of a clock signal, or the like), and performs comparison of the input voltage level by comparison of the time.

For example, U.S. Pat. No. 8,373,444 discloses a time domain-type comparator, and a sequential comparison-type A/D converter using it. The time domain-type comparator of U.S. Pat. No. 8,373,444 includes first and second voltage-time conversion circuits to which first and second input voltages and clock signals are input, and compares the first and second input voltages by comparing delay times (first and second delay times) of the clock signals in the first and second voltage-time conversion circuits. The first voltage-time conversion circuit includes a plurality of delay stages, and each delay stage includes two inverter stages. An N-type transistor is provided between a first-stage inverter and ground, and a P-type transistor is provided between a second-stage inverter and a power supply. Then, a first input voltage is input to the N-type transistor, and a second input voltage is input to the P-type transistor. The second voltage-time conversion circuit has the same configuration, but the second input voltage is input to the N-type transistor and the first input voltage is input to the P-type transistor. With such a configuration, the magnitude relation of the first and second delay times is determined according to the magnitude relation of the first and second input voltages, and voltage comparison is possible.

In the time domain-type comparator described above, the delay time (a gain for converting a voltage into a time) is determined by the number of delay stages, and there is a problem in that the number of delay stages dictates the size of the layout area. For example, in order to increase the delay time, it is necessary to increase the number of delay stages and thus the size of the layout area increases.

For example, since U.S. Pat. No. 8,373,444 is configured such that only one edge of the clock signal is delayed, the number of stages needs to be increased in order to increase the delay time. That is, in a case where one edge (a rising edge) is input to a plurality of delay stages and the edge is delayed, the next input edge is necessarily the other edge (a falling edge). Therefore, even if the outputs of a plurality of delay stages are fed back to the input side in an attempt to repeatedly perform delay, the falling edge of the second round cannot be delayed. That is, since it is not possible to feedback the outputs of a plurality of delay stages back to the input side and to repeatedly perform delay, it is necessary to increase the number of stages in order to increase the delay time.

SUMMARY

An advantage of some aspects of the invention is to provide a comparator, a circuit device, a physical quantity sensor, an electronic device, a vehicle, and the like, which can reduce a size of a layout area while securing a delay time.

The advantage can be achieved by the following configurations.

An aspect of the invention relates to a comparator including a first voltage-time conversion circuit which includes a first delay circuit, and to which a first input signal and a second input signal are input, a second voltage-time conversion circuit which includes a second delay circuit, and to which the first input signal and the second input signal are input, and a determination circuit that determines the magnitude relation of the first input signal and the second input signal, based on an output signal of the first voltage-time conversion circuit and an output signal of the second voltage-time conversion circuit, in which a first delay unit included in the first delay circuit, includes a first falling edge delay circuit that delays a falling edge of an input signal of the first delay unit, based on the first input signal, a first rising edge delay circuit that delays a rising edge of the input signal of the first delay unit, based on the second input signal, and a first output circuit that generates a first delayed output signal, based on an output signal of the first falling edge delay circuit and an output signal of the first rising edge delay circuit, and in which a second delay unit included in the second delay circuit, includes a second falling edge delay circuit that delays the falling edge of an input signal of the second delay unit, based on the second input signal, a second rising edge delay circuit that delays the rising edge of the input signal of the second delay unit, based on the first input signal, and a second output circuit that generates a second delayed output signal, based on an output signal of the second falling edge delay circuit and an output signal of the second rising edge delay circuit.

According to the aspect of the invention, the first delay unit includes a first falling edge delay circuit and a first rising edge delay circuit, and the second delay unit includes a second falling edge delay circuit and a second rising edge delay circuit. As a result, the delay circuit of each of the first delay circuit and second delay circuit can delay both the rising edge and the falling edge. Since the delay circuit can delay both edges, one edge is delayed, and the output is fed back to the input side so as to be able to delay the other edge. This makes it possible for the delay circuit to delay edges a plurality of times, thereby reducing the size of the layout area while ensuring the delay time.

In the aspect of the invention, the first falling edge delay circuit may include a first delay buffer to which an input signal of the first delay unit is input, and a first primary conductivity type transistor which is provided between a node of a first power-supply voltage and the first delay buffer, and of which a current is controlled based on the first input signal, the first rising edge delay circuit may include a second delay buffer to which an input signal of the first delay unit is input, and a first secondary conductivity type transistor which is provided between a node of a second power-supply voltage and the second delay buffer, and of which a current is controlled based on the second input signal, the second falling edge delay circuit may include a third delay buffer to which an input signal of the second delay unit is input, and a second primary conductivity type transistor which is provided between a node of the first power-supply voltage and the third delay buffer, and of which a current is controlled based on the second input signal, and the second rising edge delay circuit may include a fourth delay buffer to which an input signal of the second delay unit is input, and a second secondary conductivity type transistor which is provided between a node of the second power-supply voltage and the fourth delay buffer, and of which a current is controlled based on the first input signal.

According to the aspect of the invention with this configuration, the first delay buffer can delay the falling edge of the input signal of the first delay unit by the first primary conductivity type transistor of which current is controlled based on the first input signal. In addition, the second delay buffer can delay the rising edge of the input signal of the first delay unit by the first secondary conductivity type transistor of which current is controlled based on the second input signal. In addition, the third delay buffer can delay the falling edge of the input signal of the second delay unit by the second primary conductivity type transistor of which current is controlled based on the second input signal. In addition, the fourth delay buffer can delay the rising edge of the input signal of the second delay unit by the second secondary conductivity type transistor of which current is controlled based on the first input signal.

In the aspect of the invention, the first output circuit may include a third secondary conductivity type transistor which is provided between an output node of the first delay unit and a node of the second power-supply voltage, and of which an output signal of the first delay buffer is input to a gate, and a third primary conductivity type transistor which is provided between a node of the first power-supply voltage and an output node of the first delay unit, and of which an output signal of the second delay buffer is input to a gate, and the second output circuit may include a fourth secondary conductivity type transistor which is provided between an output node of the second delay unit and a node of the second power-supply voltage, and of which an output signal of the third delay buffer is input to a gate, and a fourth primary conductivity type transistor which is provided between a node of the first power-supply voltage and an output node of the second delay unit, and of which an output signal of the fourth delay buffer is input to a gate.

According to the aspect of the invention with this configuration, in a case where the output signal of the first delay buffer rises, the third secondary conductivity type transistor is turned on and the first delayed output signal falls. In a case where the output signal of the second delay buffer falls, the third primary conductivity type transistor is turned on and the first delayed output signal rises. In this way, the first output circuit can generate the first delayed output signal based on the output signal of the first falling edge delay circuit and the output signal of the first rising edge delay circuit. In a case where the output signal of the third delay buffer rises, the fourth secondary conductivity type transistor is turned on and the second delayed output signal falls. In a case where the output signal of the fourth delay buffer falls, the fourth primary conductivity type transistor is turned on and the second delayed output signal rises. In this way, the second output circuit can generate the second delayed output signal based on the output signal of the second falling edge delay circuit and the output signal of the second rising edge delay circuit.

In the aspect of the invention, a delay time may be controlled based on a current flowing through the first primary conductivity type transistor in the first delay buffer, a delay time may be controlled based on a current flowing through the first secondary conductivity type transistor in the second delay buffer, a delay time may be controlled based on a current flowing through the second primary conductivity type transistor in the third delay buffer, and a delay time may be controlled based on a current flowing through the second secondary conductivity type transistor in the fourth delay buffer.

According to the aspect of the invention with this configuration, at each edge, the delay time is controlled based on the current flowing through the primary conductivity type transistor or the secondary conductivity type transistor. By providing both the delay buffer provided with the primary conductivity type transistor and the delay buffer provided with the secondary conductivity type transistor, it is possible to control the delay time at both edges.

In the aspect of the invention, a delay circuit of each of the first delay circuit and the second delay circuit may include a plurality of delay units connected in series.

In this way, since each delay circuit includes a plurality of delay units, the gain for converting the voltage to time can be increased.

In the aspect of the invention, the first voltage-time conversion circuit may further include a first input signal generation circuit that generates an input signal of the first delay circuit, and a first latch circuit that operates based on an output signal of the first delay circuit, and the second voltage-time conversion circuit may further include a second input signal generation circuit that generates an input signal of the second delay circuit, and a second latch circuit that operates based on an output signal of the second delay circuit.

According to the aspect of the invention with this configuration, the first edge propagating through the delay circuit is fed back to the input of the delay circuit as the second edge by the input signal generation circuit. An edge obtained by two rounds through the delay circuit is latched by the latch circuit. In this way, since the edge makes two rounds of the delay circuit, the number of stages of the delay units can approximately be halved while maintaining the delay time.

In the aspect of the invention, the first input signal generation circuit may change an input signal of the first delay circuit from a first logic level to a second logic level, and change an input signal of the first delay circuit from the second logic level to the first logic level, in a case where an output signal of the first delay circuit changes from the first logic level to the second logic level, in which in the first latch circuit, an output signal may change from the second logic level to the first logic level, in a case where an output signal of the first delay circuit changes from the second logic level to the first logic level, in which the second input signal generation circuit may change an input signal of the second delay circuit from the first logic level to the second logic level, and change an input signal of the second delay circuit from the second logic level to the first logic level, in a case where an output signal of the second delay circuit changes from the first logic level to the second logic level, and in which in the second latch circuit, an output signal may change from the second logic level to the first logic level, in a case where an output signal of the second delay circuit changes from the second logic level to the first logic level.

According to the aspect of the invention with this configuration, after the input signal generation circuit changes the input signal of the delay circuit from the first logic level to the second logic level, the edge makes two rounds of the delay circuit, and after the delay time of two rounds, the logic level of the output signal of the latch circuit changes and the logic level of the output signal of the delay circuit changes. In this way, the edge can make two rounds of the delay circuit.

In the aspect of the invention, the first voltage-time conversion circuit may further include a first measurement circuit that measures the number of pulses of an output signal from the first delay circuit, an output signal of the first voltage-time conversion circuit may be generated based on a measurement result of the first measurement circuit, the second voltage-time conversion circuit may further include a second measurement circuit that measures the number of pulses of an output signal from the second delay circuit, and an output signal of the second voltage-time conversion circuit may be generated based on a measurement result of the second measurement circuit.

According to the aspect of the invention with this configuration, the frequency (the number of pulses per unit time) of the output signal from the delay circuit changes with the delay time according to the first input signal and the second input signal. Therefore, it is possible to determine the magnitude relation of the first input signal and the second input signal based on the number of pulses of the output signal from the delay circuit.

In the aspect of the invention, the first voltage-time conversion circuit may further include a first ring oscillator which includes the first delay circuit, and in which an output signal of the first delay circuit is fed back to an input signal, and the second voltage-time conversion circuit may further include a second ring oscillator which includes the second delay circuit, and in which an output signal of the second delay circuit is fed back to the input signal.

In this way, by configuring a ring oscillator including a delay circuit, the oscillation frequency of the ring oscillator changes according to the first input signal and the second input signal. Thus, it is possible to determine the magnitude relation of the first input signal and the second input signal based on the number of pulses of the output signal from the delay circuit.

In the aspect of the invention, the first voltage-time conversion circuit may further include a third input signal generation circuit that receives an enable signal and a signal based on an output signal of the first delay circuit, and generate an input signal of the first delay circuit, and the second voltage-time conversion circuit may further include a fourth input signal generation circuit that receives the enable signal and a signal based on an output signal of the second delay circuit, and generate an input signal of the second delay circuit.

In this way, it is possible to configure a first ring oscillator in which the output signal of the first delay circuit is fed back to the input signal and a second ring oscillator in which the output signal of the second delay circuit is fed back to the input signal.

Another aspect of the invention relates to a circuit device including the comparator according to any one described above.

Still another aspect of the invention relates to a physical quantity sensor including the circuit device described above.

Still another aspect of the invention relates to an electronic device including the circuit device described above.

Still another aspect of the invention relates to a vehicle including the circuit device described above.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of invention will be described with reference to the accompanying drawings, wherein like numbers reference like elements.

FIG. 1 shows a configuration example of a comparator of one embodiment.

FIG. 2 shows a configuration example of a first delay unit.

FIG. 3 shows a configuration example of a second delay unit.

FIG. 4 is a timing chart illustrating the operations of the first delay unit and the second delay unit.

FIG. 5 shows a first detailed configuration example of the comparator of the embodiment.

FIG. 6 is a timing chart illustrating the operation of the comparator of the first detailed configuration example, in a case of PIN>NIN.

FIG. 7 is a timing chart illustrating the operation of the comparator of the first detailed configuration example, in a case of PIN<NIN.

FIG. 8 shows a detailed configuration example of a determination circuit.

FIG. 9 is a timing chart illustrating the operation of a determination circuit, in a case of PIN>NIN.

FIG. 10 is a timing chart illustrating the operation of the determination circuit, in a case of PIN<NIN.

FIG. 11 shows a second detailed configuration example of the comparator of the embodiment.

FIG. 12 is a timing chart illustrating the operation of the second detailed configuration example of the comparator.

FIG. 13 shows a configuration example of a delay circuit of a comparative example.

FIG. 14 is a timing chart schematically illustrating the operation of the delay unit of the comparative example.

FIG. 15 shows a configuration example of a ring oscillator of the comparative example.

FIG. 16 is a timing chart schematically illustrating the operation of the ring oscillator of the comparative example.

FIG. 17 shows a dead zone of the comparator.

FIG. 18 shows a configuration example of a circuit device.

FIG. 19 shows a configuration example of a physical quantity sensor.

FIG. 20 shows a configuration example of an electronic device.

FIG. 21 schematically shows a car as a specific example of a vehicle.

DESCRIPTION OF EXEMPLARY EMBODIMENTS

Hereinafter, at least one preferred embodiment of the invention will be described in detail. It is to be noted that the embodiment described below does not unduly limit the contents of the invention described in the appended claims, and not all of the configurations described in the embodiment are necessarily indispensable as solutions of the invention.

1. Configuration

A comparator in the related art is commonly a comparator (for example, a latch comparator, or the like) that directly compares voltages (without converting the voltage into another amount such as a time). When such a comparator attempts to determine a weak signal, a preamplifier is provided in front of the comparator to amplify an input signal, and the comparator compares the amplified signal. Since it is necessary to apply a bias current to the preamplifier and the comparator, power consumption increases.

For example, when the above described comparator is applied to the sequential comparison A/D conversion circuit as illustrated later in FIG. 18, the comparator accounts for most of the power consumption. In the sequential comparison, the comparator performs comparison of a minute voltage difference, for example, by comparison of a bit close to LSB, or the like. Since the comparator has a dead zone (a range of an input voltage where a high level or a low level is stochastically determined), the comparator performs comparison after the preamplifier amplifies the voltage such that the voltage difference becomes larger than the dead zone. Therefore, the power consumption of the preamplifier tends to increase. In a case where the voltage difference to be compared by the sequential comparison-type comparator is large, the comparator is overspecified, but the preamplifier has to be designed according to the minimum voltage difference.

In the embodiment, in order to solve the above problem, a voltage-time conversion type comparator is adopted. That is, an input voltage is converted into time (a time difference in an edge) and comparison is made in that time domain. In this method, a comparator can be realized by a digital operation, so that a bias current is not necessary and low power consumption can be achieved. A comparator of one embodiment will be described below.

FIG. 1 shows a configuration example of a comparator 50 of the embodiment. FIG. 2 shows the configuration example of a delay unit UA1, and FIG. 3 shows the configuration example of a delay unit UB1. The comparator 50 includes a first voltage-time conversion circuit 10, a second voltage-time conversion circuit 20, and a determination circuit 30.

The first voltage-time conversion circuit 10 includes a first delay circuit 12, and a first input signal PIN and a second input signal NIN are input thereto. The second voltage-time conversion circuit 20 includes a second delay circuit 22, and the first input signal PIN and the second input signal NIN are input thereto. The determination circuit 30 determines the magnitude relation of the first input signal PIN and the second input signal NIN, based on the output signal NOUT of the first voltage-time conversion circuit 10 and the output signal POUT of the second voltage-time conversion circuit 20.

The first delay circuit 12 includes a delay unit UA1 (first delay unit). The delay unit UA1 includes a first falling edge delay circuit 17, a first rising edge delay circuit 18, and a first output circuit 19. The first falling edge delay circuit 17 delays the falling edge of an input signal NDLIN of the delay unit UA1, based on the first input signal PIN. The first rising edge delay circuit 18 delays the rising edge of the input signal NDLIN of the delay unit UA1, based on the second input signal NIN. The first output circuit 19 generates a first delayed output signal SQA, based on the output signal XNCLKA of the first falling edge delay circuit 17 and the output signal XPCLKA of the first rising edge delay circuit 18.

The second delay circuit 22 includes a delay unit UB1 (second delay unit). The delay unit UB1 includes a second falling edge delay circuit 27, a second rising edge delay circuit 28, and a second output circuit 29. The second falling edge delay circuit 27 delays the falling edge of the input signal PDLIN of the delay unit UB1, based on the second input signal NIN. The second rising edge delay circuit 28 delays the rising edge of the input signal PDLIN of the delay unit UB1 based on the first input signal PIN. The second output circuit 29 generates a second delayed output signal SQB, based on the output signal XNCLKB of the second falling edge delay circuit 27 and the output signal XPCLKB of the second rising edge delay circuit 28.

FIG. 1 shows a case where the delay circuits 12 and 22 respectively include a plurality of delay units UA1 to UA3, and UB1 to UB3, but without being limited thereto, the delay circuits 12 and 22 each may include one or a plurality of delay units. The number of delay units is not limited to 3. FIGS. 2 and 3 respectively show the delay units UA1 and UB1, the delay units UA2 and UA3 can be configured in the same manner as the delay unit UA1, and the delay units UB2 and UB3 can be configured in the same manner as the delay unit UB1.

Here, the first input signal PIN and the second input signal NIN are the voltages (an input voltage, a comparison voltage) to be compared by the comparator 50.

Further, the input signal NDLIN of the first delay circuit 12 and the input signal PDLIN of the second delay circuit 22 are signals having at least one edge (a change in a logical level). The signals NDLIN and PDLIN may be supplied from the outside of the voltage-time conversion circuits 10 and 20 or may be generated inside the voltage-time conversion circuits 10 and 20. For example, digital signals such as clock signals may be input as the signals NDLIN and PDLIN from the outside of the voltage-time conversion circuits 10 and 20. Alternatively, the output signals NDLQ and PDLQ of the delay circuits 12 and 22 may be processed by the logic circuits inside the voltage-time conversion circuits 10 and 20, and fed back as the signals NDLIN and PDLIN.

The output signal NOUT of the first voltage-time conversion circuit 10 is a signal based on the output signal NDLQ of the first delay circuit 12, and the output signal POUT of the second voltage-time conversion circuit 20 is a signal based on the output signal PDLQ of the second delay circuit 22. For example, the signals NDLQ and PDLQ may be directly output as the signals NOUT and POUT. Alternatively, the signals NDLQ and PDLQ may be input to a logic circuit such as a latch circuit or a counter, and the signals processed by the logic circuit may be output as the signals NOUT and POUT.

According to the embodiment, the delay units UA1 and UB1 respectively include the falling edge delay circuits 17 and 27, and the rising edge delay circuits 18 and 28. This allows the delay circuits 12 and 22 to delay both the rising edge and the falling edge. This will be described later in detail in FIG. 4.

According to the embodiment, the falling edge delay circuits 17 and 27 and the rising edge delay circuits 18 and 28 are separately configured, and the output circuits 19 and 29 output the output signals SQA and SQB based on the output signals. Since the edge not delayed (for example, the rising edge in the falling edge delay circuits 17 and 27) steeply changes, a through current in the output circuits 19 and 29 can be reduced. Further, since the edge which is not delayed steeply changes, the change of the voltage level at the delayed edge is started from the power supply level, so that the delay time can be accurately generated. This will be described later in detail in FIGS. 13 to 16, and FIG. 4.

In the embodiment, the first falling edge delay circuit 17 includes a first delay buffer DEA to which the input signal NDLIN of the delay unit UA1 is input, and a first primary conductivity type transistor TPA which is provided between a node of the first power-supply voltage (a node of the high potential side power supply VDD) and the first delay buffer DEA and of which current is controlled based on the first input signal PIN. The first rising edge delay circuit 18 includes a second delay buffer DEB to which the input signal NDLIN of the delay unit UA1 is input, and a first secondary conductivity type transistors TNA which is provided between a node of the second power-supply voltage (a node of the low potential side power supply VSS, for example, a node of ground) and the second delay buffer DEB and of which current is controlled based on the second input signal NIN. The second falling edge delay circuit 27 includes a third delay buffer DEC to which the input signal PDLIN of the delay unit UB1 is input, and a second primary conductivity type transistor TPB which is provided between a node of the first power-supply voltage and the third delay buffer DEC and of which current is controlled based on the second input signal NIN. The second rising edge delay circuit 28 includes a fourth delay buffer DED to which the input signal PDLIN of the delay unit UB1 is input, and a second secondary conductivity type transistor TNB which is provided between a node of the second power-supply voltage and the fourth delay buffer DED and of which current is controlled based on the first input signal PIN.

Here, in the control of the current based on the input signals PIN and NIN, signals based on the input signals PIN and NIN are input to the gate of the transistor, and a current (a drain current) flowing through the transistor is controlled depending on the voltage level of the signals input to the gate. That is, the transistors TPA and TPB control the current flowing from the power supply VDD to the high potential side power supply node of the delay buffers DEA and DEC based on the input signals PIN and NIN. The transistors TNA and TNB control the current flowing from the low potential side power supply node of the delay buffers DEB and DED to the power supply VSS based on the input signals PIN and NIN. Note that the input signals PIN and NIN may be directly input to the gate of the transistor, or the input signals PIN and NIN may be input to a circuit such as a buffer and the output signal of the circuit may be input to the gate of the transistor.

In addition, the primary conductivity type is one of the positive and negative conductivity types, and the secondary conductivity type is the other of the positive and negative conductivity types. For example, the primary conductivity type transistor is a P type MOS transistor and the secondary conductivity type transistor is an N type MOS transistor.

In addition, the delay buffers DEA, DEB, DEC and DED are circuits (for example, logic elements, logic circuits) that invert and output the input logic level. For example, the delay buffers DEA, DEB, DEC, and DED are inverters (logic inversion elements).

According to the embodiment, a transistor is inserted on the power supply VDD side of the delay buffers DEA and DEC. The input signals PIN and NIN of the comparator 50 are input to the gates of the transistors, and the current (the on-resistance of the transistor) flowing through the transistor is controlled based on the input signals PIN and NIN. This allows the delay buffers DEA and DEC to delay the falling edge (the rising edge in the output signal of the delay buffer). Further, a transistor is inserted on the power supply VSS side of the delay buffers DEB and DED. The input signals NIN and PIN of the comparator 50 are input to the gates of the transistors, and the current (the on-resistance of the transistor) flowing through the transistor is controlled based on the input signals NIN and PIN. This allows the delay buffers DEB and DED to delay the rising edge (the falling edge in the output signal of the delay buffer). In this way, the delay units UA1, UB1 are able to delay both the rising edge and the falling edge.

In the embodiment, the first output circuit 19 includes a third secondary conductivity type transistor TNC which is provided between the output node of the delay unit UA1 and the node of the second power-supply voltage (the node of the power supply VSS), and of which the output signal XNCLKA of the first delay buffer DEA is input to a gate, and a third primary conductivity type transistor TPC which is provided between the node of the first power-supply voltage (the node of the power supply VDD) and the output node of the delay unit UA1, and of which the output signal XPCLKA of the second delay buffer DEB is input to a gate. The second output circuit 29 includes a fourth secondary conductivity type transistor TND which is provided between the output node of the delay unit UB1 and the node of the second power-supply voltage, and of which the output signal XNCLKB of the third delay buffer DEC is input to a gate, and a fourth primary conductivity type transistor TPD which is provided between the node of the first power-supply voltage and the output node of the delay unit UB1, and of which the output signal XPCLKB of the fourth delay buffer DED is input to a gate.

According to the embodiment, in a case where the input signals NDLIN and PDLIN of the delay units UA1 and UB1 fall, the output signals XNCLKA and XNCLKB of the delay buffers DEA and DEC rise, the transistors TNC and TND are turned on, and the delayed output signals SQA and SQB fall. In a case where the input signals NDLIN and PDLIN of the delay units UA1 and UB1 rise, the output signals XPCLKA and XPCLKB of the delay buffers DEB and DED rise, the transistors TPC and TPD are turned on, and the delayed output signals SQA and SQB rise. In this way, the output circuits 19 and 29 generate the delayed output signals SQA and SQB, based on the output signals XNCLKA and XNCLKB of the falling edge delay circuits 17 and 27 and the output signals XPCLKA and XPCLKB of the rising edge delay circuits 18 and 28.

FIG. 4 is a timing chart illustrating operations of the delay units UA1 and UB1. Here, the case of PIN>NIN will be described as an example. The input signal of the delay unit is not limited to the example in FIG. 4. For example, the rising edge may be input after the falling edge, or a signal like a clock signal in which rectangular waves repeat may be input.

As indicated by E1 and E2 in FIG. 4, in a case where the input signals NDLIN and PDLIN of the delay units UA1 and UB1 go to the high level from the low level, as indicated by E3 and E4, the output signals XPCLKA and XPCLKB of the delay buffers DEB and DED go to the low level from the high level. At this time, since PIN>NIN, the current flowing through the transistor TNA in the delay unit UA1 in FIG. 2 becomes smaller than the current flowing through the transistor TNB in the delay unit UB1 in FIG. 3. Therefore, the time when the output signal XPCLKA of the delay buffer DEB changes from a high level to a low level becomes longer than the time when the output signal XPCLKB of the delay buffer DED changes from a high level to a low level. As a result, as indicated by E5 and E6, the timing at which the transistor TPC is turned on and the delayed output signal SQA goes to the high level from the low level becomes later than the timing at which the transistor TPD is turned on and the delayed output signal SQB goes to the high level from the low level.

Similarly, as indicated by E7 and E8, in a case where the input signals NDLIN and PDLIN of the delay units UA1 and UB1 go to the low level from the high level, as indicated by E9 and E10, the output signals XNCLKA and XNCLKB of the delay buffers DEA and DEC go to the high level from the low level. At this time, since PIN>NIN, the current flowing through transistor TPA in delay unit UA1 in FIG. 2 becomes smaller than the current flowing in transistor TPB in the delay unit UB1 in FIG. 3. Therefore, the time when the output signal XNCLKA of the delay buffer DEA changes from the low level to the high level is longer than the time when the output signal XNCLKB of the delay buffer DEC changes from the low level to the high level. Thus, as shown by E11 and E12, the timing at which the transistors TNC is turned on and the delayed output signal SQA goes to the low level from the high level becomes later than the timing at which the transistor TND is turned on and the delayed output signal SQB goes to the low level from the high level.

In a case of PIN<NIN, the timing at which the delayed output signal SQA goes to the high level from the low level becomes earlier than the timing at which the delayed output signal SQB goes to the high level from the low level. The timing at which the delayed output signal SQA goes to the low level from the high level becomes earlier than the timing at which the delayed output signal SQB goes to the low level from the high level.

As described above, in the embodiment, since the delay units UA1 and UB1 can delay both edges, it is possible to reduce the number of stages of the delay unit and to reduce the layout area of the comparator 50. For example, as illustrated in FIG. 5 to FIG. 7, since the input signal generation circuits 14 and 24 are provided and an edge makes two rounds of the delay circuits 12 and 22, the delay time can be approximately doubled. At this time, the falling edge and the rising edge in this order are propagated through the delay circuits 12 and 22 and delayed, but this is realized by delaying both edges. As illustrated in FIG. 11 and FIG. 12, the delay circuits 12 and 22 may be incorporated in the ring oscillator. In this case, the oscillation signal (clock signal) of the ring oscillator propagates through the delay circuits 12 and 22, and the oscillation frequency differs according to the delay. This is also realized by delaying both edges. In this way, since both edges can be delayed, it is possible to generate delays a plurality of times by the delay circuits 12 and 22, thereby increasing the delay time while reducing the number of stages.

In the embodiment, in the first delay buffer DEA, a delay time is controlled based on a current flowing through the first primary conductivity type transistor TPA. In the second delay buffer DEB, a delay time is controlled based on a current flowing through the first secondary conductivity type transistor TNA. In the third delay buffer DEC, a delay time is controlled based on a current flowing through the second primary conductivity type transistor TPB. In the fourth delay buffer DED, a delay time is controlled based on a current flowing through the second secondary conductivity type transistors TNB.

That is, in a case where the inputs of the delay buffers DEA and DEC fall from the high level to the low level, the output rises from the low level to the high level due to the current flowing through the primary conductivity type transistors TPA and TPB. In this case, the delay time of the rising edge of the output is determined by the current flowing through the primary conductivity type transistors TPA and TPB according to the signals PIN and NIN. On the other hand, in a case where the inputs of the delay buffers DEB and DED rise from the low level to the high level, the output falls from the high level to the low level due to the current flowing through the secondary conductivity type transistors TNA and TNB. In this case, the delay time of the falling edge of the output is determined by the current flowing through the secondary conductivity type transistors TNA and TNB according to the signals NIN and PIN. Note that the delay time may be controlled by directly supplying the current flowing through the transistor to the power supply node of the delay buffer, or the delay time may be controlled by supplying the current flowing through the transistor to the power supply node of the delay buffer through some circuits or elements.

In this way, at each edge, the delay time is controlled based on the current flowing through the primary conductivity type transistor or the secondary conductivity type transistor. By providing both the delay buffer provided with the primary conductivity type transistor and the delay buffer provided with the secondary conductivity type transistor, it is possible to control the delay time at both edges.

2. First Detailed Configuration

FIG. 5 shows a first detailed configuration example of the comparator 50 in the embodiment. In FIG. 5, the first voltage-time conversion circuit 10 includes a first delay circuit 12, a first input signal generation circuit 14, and a first latch circuit 16, and the second voltage-time conversion circuit 20 includes a second delay circuit 22, a second input signal generation circuit 24, and a second latch circuit 26.

A delay circuit of each of the first delay circuit 12 and the second delay circuit 22 includes a plurality of delay units connected in series. Each delay unit is the delay unit shown in FIGS. 2 and 3. Here, being connected in series means that the output signal of the delay unit becomes the input signal of the next delay unit. In FIG. 5, the case where the delay circuits 12 and 22 each has three delay units is shown, but it is not limited to this.

In this way, each delay circuit includes a plurality of delay units, such that the gain for converting the voltage to time can be increased. In the embodiment, since the edges are delayed twice by the delay circuits 12 and 22, it is possible to realize the same gain as in the case of delaying the edge only once, with about half the number of delay units.

The first input signal generation circuit 14 generates an input signal NDLIN of the first delay circuit 12, and outputs the input signal NDLIN to the first delay circuit 12. The first latch circuit 16 is a latch circuit operating based on the output signal NDLQ of the first delay circuit 12. The second input signal generation circuit 24 generates an input signal PDLIN of the second delay circuit 22, and outputs the input signal PDLIN to the second delay circuit 22. The second latch circuit 26 is a latch circuit operating based on the output signal PDLQ of the second delay circuit 22.

Specifically, the first input signal generation circuit 14 includes an RS latch RSA in which an enable signal EN is input to a set terminal and an output signal NDLQ of the delay circuit 12 is input to a reset terminal, and a NAND circuit (negative AND circuit) NAA in which the enable signal EN and the output signal RSAQ of the RS latch RSA are input. The output signal of the NAND circuit NAA is the input signal NDLIN of the delay circuit 12. The second input signal generation circuit 24 includes an RS latch RSB in which the enable signal EN is input to a set terminal and an output signal PDLQ of the delay circuit 22 is input to a reset terminal, and a NAND circuit NAB in which the enable signal EN and the output signal RSBQ of the RS latch RSB are input. The output signal of the NAND circuit NAB is the input signal PDLIN of the delay circuit 22. The enable signal EN is input from, for example, the control circuit and the processing circuit included in the circuit device including the comparator. Alternatively, the enable signal EN may be input from a CPU or the like provided outside the circuit device including the comparator.

The latch circuits 16 and 26 are, for example, flip-flop circuits. The enable signal EN is input to the reset terminal (low active) of the latch circuit 16, the first logic level (for example, the high level) is input to the data terminal, and the output signal NDLQ of the delay circuit 12 is input to the clock terminal. The output signal of the latch circuit 16 is the output signal NOUT of the voltage-time conversion circuit 10. The enable signal EN is input to the reset terminal (low active) of the latch circuit 26, the first logic level (for example, the high level) is input to the data terminal, and the output signal PDLQ of the delay circuit 22 is input to the clock terminal. The output signal of the latch circuit 26 is the output signal POUT of the voltage-time conversion circuit 20. Note that the latch circuits 16 and 26 are not limited to the flip-flop circuits, and any circuit may be used as long as the circuit fetches the input signal and outputs the fetched signal.

With such a configuration, the first edges propagating through the delay circuits 12 and 22 are fed back to the inputs of the delay circuits 12 and 22 as the second edges by the input signal generation circuits 14 and 24. Then, the edges obtained by two rounds through the delay circuits 12 and 22 are latched by the latch circuits 16 and 26. In this way, since the edge makes two rounds of the delay circuits 12 and 22, the number of stages of the delay units can approximately be halved while maintaining the delay time.

FIG. 6 is a timing chart illustrating the operation of the comparator 50 of FIG. 5, in a case of PIN>NIN.

As indicated by A1 of FIG. 6, the first input signal generation circuit 14 changes the input signal NDLIN of the first delay circuit 12 from a high level (a first logic level) to a low level (a second logic level). That is, as indicated by A2, the enable signal EN changes from the low level to the high level, whereby the output signal (input signal NDLIN) of the NAND circuit NAA changes from the high level to the low level.

As indicated by A3, the falling edge of the input signal NDLIN propagates through the delay circuit 12, and the output signal NDLQ of the delay circuit 12 changes from the high level to the low level. In this case, as indicated by A4, the input signal generation circuit 14 changes the input signal NDLIN of the delay circuit 12 from the low level to the high level. That is, as indicated by A5, the RS latch RSA is reset by the output signal NDLQ becoming the low level, and the output signal RSAQ of the RS latch RSA changes from the high level to the low level. As the output signal RSAQ of the RS latch RSA goes to the low level, the output signal (the input signal NDLIN) of the NAND circuit NAA changes from the low level to the high level.

As indicated by A6, the rising edge of the input signal NDLIN propagates through the delay circuit 12, and the output signal NDLQ of the delay circuit 12 changes from the low level to the high level. In this case, the first latch circuit 16 changes the output signal NOUT from a low level to a high level. That is, when the enable signal EN is the high level, the latch circuit 16 is released from reset. When the input signal (the output signal NDLQ) of the clock terminal rises, the input signal (high level) of the data terminal is fetched and the output signal NOUT changes from the low level to the high level.

In this way, the edge makes two rounds of the delay circuit 12 after the enable signal EN goes to the high level, and the output signal NOUT goes to the high level after the delay time TDN.

The operation of the second voltage-time conversion circuit 20 is the same. That is, the second input signal generation circuit 24 changes the input signal PDLIN of the second delay circuit 22 from a high level to a low level. In a case where the output signal PDLQ of the delay circuit 22 changes from the high level to the low level, the input signal generation circuit 24 changes the input signal PDLIN of the delay circuit 22 from the low level to the high level. In a case where the output signal PDLQ of the delay circuit 22 is changed from the low level to the high level, the second latch circuit 26 changes the output signal POUT from the low level to the high level. In this way, the edge makes two rounds of the delay circuit 22 after the enable signal EN goes to the high level, and the output signal POUT goes to the high level after the delay time TDP.

In the case of PIN>NIN, it is established that TDP<TDN, the output signal POUT rises earlier than the output signal NOUT. In a case where it is detected that the output signal POUT rises earlier, the determination circuit 30 determines that PIN>NIN, and outputs the determination result (for example, a determination signal CPQ of a high level).

FIG. 7 is a timing chart illustrating the operation of the comparator 50 of FIG. 5, in a case of PIN<NIN. Since the operation is the same as in FIG. 6, the description thereof will be omitted.

In the case of PIN<NIN, it is established that TDP>TDN, the output signal NOUT rises earlier than the output signal POUT. In a case where it is detected that the output signal NOUT rises earlier, the determination circuit 30 determines that PIN<NIN, and outputs the determination result (for example, a determination signal CPQ of a low level).

3. Determination Circuit

FIG. 8 is a detailed configuration example of the determination circuit 30. The configuration of the determination circuit 30 is not limited to the example in FIG. 8, but any circuit may be used as long as the circuit is able to determine that the edge is output earlier than either the signal NOUT or the signal POUT.

The determination circuit 30 of FIG. 8 includes buffers BFE1 and BFE2 that delay the signals NOUT and POUT, an RS latch RSE1 to which the output signals of the buffers BFE1 and BFE2 are input, an AND circuit ANE (logical product circuit) that outputs a logical product of the signals NOUT and POUT, an OR circuit ORE (logical sum circuit) that outputs a logical sum of the output signals of the buffers BFE1 and BFE2, and an RS latch RSE2 to which the output signals of the AND circuit ANE and the OR circuit ORE are input.

The output signal of the RS latch RSE1 is the determination signal CPQ. In the case of PIN>NIN, the determination signal CPQ goes to a high level, and in the case of PIN<NIN, the determination signal CPQ goes to a low level.

The output signal LATCH of the OR circuit ORE goes to a high level (active) in a case where any of the signals NOUT and POUT goes to the high level (that is, in a case where the determination is confirmed).

The output signal of the RS latch RSE2 is a minute determination flag signal SFLAG indicating whether or not the voltage difference (time difference between the signals POUT and NOUT) between the signals PIN and NIN is minute. In a case where the voltage difference is minute, the signal SFLAG goes to the high level (active), and in a case where the voltage difference is not minute, the signal SFLAG goes to the low level. In a case where the voltage difference between the signals PIN and NIN is small, the comparator 50 has a dead zone of magnitude comparison (a range where a determination result is stochastically determined, as will be described later). For example, the voltage difference determined to be minute is set to the extent of the dead zone. In a case where the signal SFLAG is at a high level, magnitude comparison is made a plurality of times for the same signals PIN and NIN. This makes it possible to substantially reduce the dead zone.

FIG. 9 is a timing chart illustrating the operation of the determination circuit 30, in a case of PIN>NIN. PIN>>NIN indicates that the signal PIN is a voltage sufficiently larger than the signal NIN (not a minute signal).

First, the size determination of the signals PIN and NIN will be described. As indicated by B1 in FIG. 9, the signal POUT goes to a high level from a low level earlier than the signal NOUT. Then, as indicated by B2, the RS latch RSE1 latches the high level after the delay time by the buffer BFE2, and the determination signal CPQ is determined to be the high level. This determination operation is the same regardless of whether or not it is a minute signal.

Next, the minute determination flag signal SFLAG will be described. First, a case where it is not a minute signal will be described. As indicated by B3, the signal LATCH goes to the high level from the low level after the delay time DLB by the buffer BFE2 since the signal POUT goes to the high level. In the case of PIN>>NIN, when the signal LATCH goes to the high level, the signal NOUT is at the low level as indicated by B4 (since the time difference is large, it does not go to the high level). Therefore, the output signal of the AND circuit ANE is at a low level, the RS latch RSE2 latches the low level as indicated by B5, and the signal SFLAG is determined to be the low level.

Next, a case of a minute signal will be described. As indicated by B10, the time difference between the falling edges of the signals POUT and NOUT is smaller than the delay time DLB by the buffer BFE2. In this case, when the signal LATCH goes to the high level, the signal NOUT is at the high level as indicated by B11. Therefore, the output signal of the AND circuit ANE is at a high level, the RS latch RSE2 latches the high level as indicated by B12, and the signal SFLAG is determined to be the high level.

FIG. 10 is a timing chart illustrating the operation of the determination circuit 30, in a case of PIN<NIN. PIN<<NIN indicates that the signal NIN is a voltage sufficiently larger than the signal PIN (not a minute signal).

Since the operation is the same as in the case of PIN>NIN, the outline will be described. In the case of PIN<NIN, since the signal NOUT goes to a high level from a low level earlier than the signal POUT, the RS latch RSE1 latches the low level after the delay time by the buffer BFE1 and the determination signal CPQ is determined to be the low level.

In a case where it is not a minute signal, the signal LATCH goes to the high level from the low level after the delay time DLC by the buffer BFE1 since the signal NOUT goes to the high level, the RS latch RSE2 latches the low level, and the signal SFLAG is determined to be the low level. In the case of a minute signal, the time difference between the falling edges of the signals POUT and NOUT is smaller than the delay time DLC by the buffer BFE1. In this case, when the signal LATCH goes to the high level, the RS latch RSE2 latches the high level and the signal SFLAG is determined to be the high level.

4. Second Detailed Configuration

FIG. 11 shows a second detailed configuration example of the comparator 50 of the embodiment. In FIG. 11, the first voltage-time conversion circuit 10 includes a first delay circuit 12, a third input signal generation circuit 11, and a first measurement circuit 15, and the second voltage-time conversion circuit 20 includes a second delay circuit 22, a fourth input signal generation circuit 21, and a second measurement circuit 25.

The first measurement circuit 15 measures the number of pulses of the output signal NDLQ from the first delay circuit 12. The output signal NOUT of the first voltage-time conversion circuit 10 is generated based on the measurement result of the first measurement circuit 15. The second measurement circuit 25 measures the number of pulses of the output signal PDLQ from the second delay circuit 22. The output signal POUT of the second voltage-time conversion circuit 20 is generated based on the measurement result of the second measurement circuit 25. The determination circuit 30 determines the magnitude relation of the first input signal PIN and the second input signal NIN, based on the measurement results (signals NOUT and POUT based on the measurement results) from the first measurement circuit 15 and the second measurement circuit 25.

For example, the measurement circuits 15 and 25 are counters that count the number of pulses of the signals NDLQ and PDLQ, and set the signals NOUT and POUT to the high level in a case where the count value reaches a predetermined value. The measurement circuits 15 and 25 are not limited to counters, and may be any circuit as long as the circuit can convert the number of pulses of signals NDLQ and PDLQ into signals NOUT and POUT. For example, the measurement circuits may be shift registers in which bits are shifted by pulses of the signals NDLQ and PDLQ.

A delay circuit of each of the first delay circuit 12 and the second delay circuit 22 includes, for example, a delay unit of only one stage. Alternatively, each delay circuit may be a plurality of delay units connected in series.

According to the embodiment, the frequencies (the number of pulses per unit time) of the output signals NDLQ and PDLQ from the delay circuits 12 and 22 change with delay times according to the signals PIN and NIN. This makes it possible to determine the magnitude relation of the signals PIN and NIN based on the number of pulses of the signals NDLQ and PDLQ.

In the embodiment, the first voltage-time conversion circuit 10 includes a first ring oscillator in which the output signal NDLQ of the first delay circuit 12 is fed back to the input signal NDLIN. The second voltage-time conversion circuit 20 includes a second ring oscillator in which the output signal PDLQ of the second delay circuit 22 is fed back to the input signal PDLIN.

The first ring oscillator corresponds to a loop configured with the third input signal generation circuit 11 and the first delay circuit 12. The second ring oscillator corresponds to a loop configured with the fourth input signal generation circuit 21 and the second delay circuit 22.

In this way, by configuring the ring oscillator including the delay circuits 12 and 22, the oscillation frequency of the ring oscillator varies according to the signals PIN and NIN. This makes it possible to determine the magnitude relation of the signals PIN and NIN based on the number of pulses of the signals NDLQ and PDLQ.

In the embodiment, the third input signal generation circuit 11 receives the enable signal EN and the signal based on the output signal NDLQ of the first delay circuit 12, and generates the input signal NDLIN of the first delay circuit 12. The fourth input signal generation circuit 21 receives the enable signal EN and the signal based on the output signal PDLQ of the second delay circuit 22, and generates the input signal PDLIN of the second delay circuit 22.

For example, the input signal generation circuits 11 and 21 are NAND circuits (negative logical product circuit). In this case, if the enable signal EN goes to the high level, the NAND circuit functions in the same way as the inverter for the signals NDLQ and PDLQ. That is, ring oscillators (delay units UA1 and UA2 are not logically inverted) by odd-numbered inverted logic circuits are configured.

With such a configuration, it is possible to configure a first ring oscillator in which the output signal NDLQ of the first delay circuit 12 is fed back to the input signal NDLIN, and a second ring oscillator in which the output signal PDLQ of the second delay circuit 22 is fed back to the input signal PDLIN.

In FIG. 11, the signals based on the output signals NDLQ and PDLQ of the delay circuits 12 and 22 are the output signals NDLQ and PDLQ of the delay circuits 12 and 22. However, without being limited thereto, signals based on the signals NDLQ and PDLQ may be signals obtained by processing the signals NDLQ and PDLQ by some elements or circuits.

FIG. 12 is a timing chart illustrating the operation of the second detailed configuration example of the comparator 50. FIG. 12 illustrates the case where the predetermined value of the count value is “4”, but the predetermined value is not limited to “4”.

As indicated by F1 in FIG. 12, if the enable signal EN goes to the high level from the low level, the ring oscillator starts oscillating. In the case of PIN>NIN, since the delay time of the first delay circuit 12 is larger than that of the second delay circuit 22, the oscillation frequency of the first ring oscillator is lower than that of the second ring oscillator (the number of pulses of the signal NDLQ per unit time decreases). Therefore, as indicated by F2, the count value of the second measurement circuit 25 reaches the predetermined value “4” earlier than the count value of the first measurement circuit 15, and the signal POUT goes to the high level from the low level earlier than the signal NOUT.

In a case of PIN<NIN, since the oscillation frequency of the second ring oscillator is lower than that of the first ring oscillator, the count value of the first measurement circuit 15 reaches a predetermined value earlier than the count value of the second measurement circuit 25, and the signal NOUT goes to the high level from the low level earlier than the signal POUT.

5. Regarding Through Current and Delay Time of Delay Unit

Hereinafter, the delay unit's ability to reduce the through current and realize an accurate delay time will be described.

FIG. 13 shows a configuration example of a delay unit of the comparative example. In the comparative example, a delay unit configured with transistors TPH1, TPH2, TNH1, and TNH2 and a delay unit configured with transistors TPH3, TPH4, TNH3, and TNH4 are connected in series. The transistors TPH2, TNH2, TPH4 and TNH4 constitute an inverter, and the delay at the inverter is set by the transistors TPH1, TNH1, TPH3, and TNH3.

FIG. 14 is a timing chart schematically illustrating the operation of the comparative example in FIG. 13. The input signal CLK schematically shows the signal propagating through the delay circuit 12 in the comparator 50 of FIG. 5 or FIG. 11. The signal OUT (after buffer) is the output signal of the buffer in a case where it is assumed that a buffer is provided at the next stage of the delay unit in FIG. 13.

If the signal CLK falls as indicated by D1 in FIG. 14, the signal XOUT gradually changes from the low level to the high level by the transistor TPH1 as indicated by D2, and the signal OUT gradually changes from the high level to the low level by the transistor TNH3 as indicated by D3. The falling edge of the signal OUT (after buffer) is delayed from the falling edge of the signal CLK. If the signal CLK rises as indicated by D5, the signal XOUT gradually changes from the high level to the low level by the transistor TNH1 as indicated by D6, and the signal OUT gradually changes from the low level to the high level by the transistor TPH3 as indicated by D7. The rising edge of the signal OUT (after buffer) is delayed from the rising edge of the signal CLK.

In this way, the falling edge and the rising edge can be delayed in the comparative example of FIG. 13. However, since transistors are inserted in both the high potential side power supply and the low potential side power supply of each of the inverters, the falling edge and the rising edge of the output signals (XOUT, OUT) gradually change. If the transition period of the voltage level becomes long in this way, there is a possibility that the through current flowing in the transition period increases in a logic circuit (for example, a delay unit, an inverter, a buffer, or the like) to which the signal is input.

In this regard, in the embodiment, as illustrated in FIG. 2, the transistor is inserted only in one of the high potential side power supply and the low potential side power supply of the inverters (delay buffers DEA and DEB). Therefore, both the transistors TPC and TNC of the output circuit 19 are turned off in the transition period of the voltage level, and the through current can be reduced.

Specifically, as indicated by E20 of FIG. 4, the signal XNCLKA immediately falls when the input signal NDLIN of the delay unit rises. This is because a transistor is not inserted in the low potential side power supply of the delay buffer DEA. At this time, both the transistors TPC and TNC of the output circuit 19 are turned off. Thereafter the signal XPCLKA goes to the low level, the transistor TPC is turned on, and the signal SQA rises. Similarly, as indicated by E21, the signal XPCLKA immediately rises when the input signal NDLIN of the delay unit falls. This is because a transistor is not inserted in the high potential side power supply of the delay buffer DEB. At this time, both the transistors TPC and TNC of the output circuit 19 are turned off. Thereafter the signal XNCLKA goes to the high level, the transistor TNC is turned on, and the signal SQA falls. In this way, there is a period during which both the transistors TPC and TNC are turned off, such that the through current due to simultaneous turning-on of the transistors TPC and TNC is not generated.

FIG. 15 shows a configuration example of the ring oscillator of the comparative example. The ring oscillator of the comparative example includes a delay unit of one stage in FIG. 13, and the oscillation frequency of the ring oscillator changes as the delay time in the delay unit changes according to the signals PIN and NIN.

FIG. 16 is a timing chart schematically illustrating the operation of the comparative example in FIG. 15. The input signal CLK corresponds to enable signal EN in the comparator 50 in FIG. 11.

As indicated by G1 in FIG. 16, if the signal CLK goes to the high level from the low level, the ring oscillator starts oscillating. As indicated by G2, the output signal XCLK of the delay buffer gradually goes to the high level from the low level. At this time, as indicated by G3, since the signal OUT falls at the time when the signal XCLK reaches the logical threshold voltage of the inverter, the signal XCLK starts to smoothly change to a low level before reaching the high level (the voltage level of the power supply VDD). Similarly, the signal OUT falls before the signal XCLK reaches the low level (the voltage level of the power supply VSS), and the signal XCLK starts to smoothly change to a high level.

By repeating the change of the signal XCLK as described above, the signal XCLK is reciprocated around the logical threshold voltage of the inverter as indicated by G4. Therefore, as compared with the case where the change of the signal XCLK is started from the power supply level, the signal XCLK reaches the logical threshold voltage in a short time, and the delay time in the delay unit becomes shorter than assumed. Then, a difference between the oscillation frequencies of the first voltage-time conversion circuit 10 and the second voltage-time conversion circuit 20 becomes smaller than assumed, and the gain for converting the voltage difference between the signals PIN and NIN into the oscillation frequency difference is reduced. If the gain is reduced in this way, it seems that the minute signal (in a case where the voltage difference between the signals PIN and NIN is weak) is not sufficiently amplified and the dead zone of the comparator 50 is substantially enlarged. Therefore, the determination accuracy for the minute signal is lowered.

In this regard, in the embodiment, the transistor is inserted only in one of the high potential side power supply and the low potential side power supply of the inverters (delay buffers DEA and DEB). Therefore, it quickly reaches the power level of the side where the transistor is not inserted, and the change of the signal can be started from the power level when the delay is generated next.

Specifically, as indicated by E7 in FIG. 4, the falling edge of the signal NDLIN is delayed by the output signal XNCLKA of the delay buffer DEA as indicated by E9. As indicated by E1, at the rising edge of the preceding signal NDLIN, the signal XNCLKA steeply goes to the low level as indicated by E20. This is because a transistor is not inserted in the low potential side power supply of the delay buffer DEA. Thus, the change of the signal XNCLKA can necessarily be started from the low level (the voltage level of the power supply VSS) as shown at E9. Similarly, as indicated by E22, the rising edge of the signal NDLIN is delayed by the output signal XPCLKA of the delay buffer DEB as indicated by E23. As indicated by E7, at the falling edge of the preceding signal NDLIN, the signal XPCLKA steeply goes to the high level as indicated by E21. This is because a transistor is not inserted in the high potential side power supply of the delay buffer DEB. Thus, the change of the signal XPCLKA can necessarily be started from the high level (the voltage level of the power supply VDD) as shown at E23.

In this way, in the embodiment, the delay time in the delay unit is accurately realized. In a case where the delay unit is applied to a ring oscillator, a gain for converting the voltage difference between the signals PIN and NIN into a difference between the oscillation frequencies can be accurately realized.

6. With Regard to Dead Zone of Comparator

FIG. 17 is a diagram illustrating a dead zone of the comparator. The voltage input to the positive terminal of comparator is set to VP, and the voltage input to the negative terminal is set to VN. In FIG. 17, the horizontal axis represents the voltage Vin=VP−VN, and the vertical axis represents the probability that the output of the comparator goes to a high level.

Here, the comparator is considered as a model. That is, a model is considered in which a voltage VP+Vn is input to the positive terminal of a comparator without a dead zone and a voltage VN is input to the negative terminal. The absence of a dead zone means that the output is determined to be the high level (100%) in a case of VP>VN, and the output is determined to be the low level (100%) in a case of VP<VN. The voltage Vn is a noise according to a normal distribution in which the average value is zero and the variance is the square ofσ. In this case, the probability f(Vin) that the output of the comparator goes to a high level is a cumulative distribution function like the following Expression (1). Here, erf( ) is an error function.

$\begin{matrix} {{f({Vin})} = {\frac{1}{2}\left( {1 + {{erf}\left( \frac{Vin}{\sqrt{2\sigma^{2}}} \right)}} \right)}} & (1) \end{matrix}$

Since the right side of Expression (1) is a function of Vin/σ, the same probability f(Vin) is obtained if Vin/σ is the same.

As illustrated in FIG. 17, for example, the voltage range of −σ≤Vin≤+σ (so-called 1 sigma) is defined as a dead zone. In this voltage range, the probability that the output of comparator goes to a high level is in the range of 15.9% or more and 84.1% or less.

In FIG. 16, it is described that the delay time in the delay unit becomes shorter and the dead zone of the comparator is widened, in the ring oscillator of the comparative example. This will be described by using the above model. That is, shortening of the delay time means that the gain of the voltage-time conversion decreases, but corresponds to the fact that the difference (Vin) of the input voltage is substantially reduced on the input side of the comparator. Then, σ of the noise voltage Vn appears relatively large. That is, in FIG. 17, +σ on the horizontal axis moves to the positive side, −σ moves to the negative side, and the dead zone is expanded.

In the delay unit of the embodiment, since the delay time as described above is not shortened, the dead zone of the comparator is not increased. If the dead zone increases, the determination accuracy of the minute signal decreases, but, the determination can be made at a high determination accuracy, by using the delay unit of the embodiment.

In addition, in FIG. 8, the minute determination flag signal SFLAG is described. By setting the delay time of the buffers BFE1 and BFE2 such that the signal SFLAG becomes active in a case where the voltage Vin is within the range of the dead zone, it becomes possible to know that the input voltage is within the range of the dead zone, and to take various countermeasures accordingly.

7. Circuit Device

FIG. 18 is a configuration example of the circuit device 100 including the comparator 50 of the embodiment. Here, a configuration example of a sequential comparison type A/D conversion circuit is illustrated as an example of the circuit device 100. In addition, the circuit device 100 is not limited to this configuration, and may include the comparator 50.

The circuit device 100 includes a comparator 50, a control unit 120 (a control circuit), a sample and hold circuit 130 (an S/H circuit), and a D/A conversion circuit 140 (DAC).

The sample and hold circuit 130 samples and holds the input voltage VIN and outputs the held voltage SIN. The control unit 120 outputs the sequential comparison data RDA stored in a sequential comparison register 121 to the D/A conversion circuit 140. The D/A conversion circuit 140 performs D/A conversion of the sequential comparison data RDA, and outputs the converted voltage DQ. The comparator 50 compares the magnitude of the voltage SIN with the magnitude of the voltage DQ, and outputs the determination signal CPQ. That is, in FIG. 18, the voltages SIN and DQ correspond to the signals PIN and NIN in FIG. 1 or the like. The control unit 120 updates the sequential comparison data RDA stored in the sequential comparison register 121 based on the determination signal CPQ. The control unit 120 repeatedly updates such sequential comparison data RDA, and outputs finally obtained sequential comparison data RDA as A/D conversion data DOUT.

8. Physical Quantity Sensor

FIG. 19 is a configuration example of a physical quantity sensor 400 including the circuit device 100 of the embodiment. Here, a configuration example of a vibration gyro sensor (angular velocity sensor) is illustrated as an example of the physical quantity sensor 400. In addition, the physical quantity sensor 400 is not limited to this configuration, and the circuit device 100 of the embodiment can be applied to various physical quantity sensors such as a capacitance type (silicon MEMS type) gyro sensor, an acceleration sensor, a pressure sensor, and a temperature sensor.

The physical quantity sensor 400 includes a vibrator 410 (for example, a quartz vibrator) which is a detection element that detects the Coriolis force according to an angular velocity, and a circuit device 100 that drives the vibrator 410 and performs a process of detecting the angular velocity.

The circuit device 100 includes a driving circuit 420 and a detection circuit 430. The driving circuit 420 applies a driving signal of a sinusoidal wave or a rectangular wave to a driving vibration portion of the vibrator 410, and automatically adjusts the amplitude of the driving signal constantly based on the feedback signal from the driving vibration portion. The detection circuit 430 includes an analog front end circuit 432 (AFE), an A/D conversion circuit 434, and a processing circuit 436. The analog front end circuit 432 performs charge voltage conversion (Q/V conversion) on the detection signal from the vibrator 410, and synchronously detects the voltage to extract the angular velocity signal. The A/D conversion circuit 434 performs A/D conversion of the angular velocity signal into angular velocity data. The A/D conversion circuit 434 includes the comparator 50 of the embodiment, and corresponds to the sequential comparison type A/D conversion circuit described in FIG. 18. The processing circuit 436 performs various digital signal processes on the angular velocity data, and outputs the processed angular velocity data. For example, a temperature compensation process, a zero point correction process, a digital filter process, or like are performed as digital signal processes.

9. Electronic Device

FIG. 20 and FIG. 21 are examples of an electronic device and a vehicle including the circuit device 100 of the embodiment. The circuit device 100 of the embodiment can be incorporated into, for example, various vehicles such as a car, an airplane, a motorbike, a bicycle, and a ship. A vehicle is, for example, equipment or a device that moves on the ground, the sky or the sea, equipped with a drive mechanism such as an engine or a motor, a steering mechanism such as a steering wheel or a rudder, and various electronic devices.

FIG. 20 is a configuration example of an electronic device 300. A digital still camera, a biometric information detection device (a wearable health device, for example, a pulsimeter, a pedometer, an activity meter, or the like), or a robot (a running robot, or a walking robot) can be assumed as a specific example of the electronic device 300. Here, the case where the electronic device 300 includes the physical quantity sensor 400 is described as an example, but the invention is not limited thereto. That is, the electronic device 300 may include the circuit device 100, and can be applied to various electronic devices in addition thereto.

The electronic device 300 includes a processing unit 310 (for example, a processor such as a CPU or a gate array), a storage unit 320 (for example, a memory, a hard disk, or the like), an operation unit 330 (an operation device), an interface unit 340 (an interface circuit or an interface device), a display unit 350 (display), and a physical quantity sensor 400.

The display unit 350 is, for example, a liquid crystal display device, or an electro-luminescence (EL) display device using a self-luminous element. The operation unit 330 is a user interface that accepts various operations from the user. For example, the operation unit 330 is a button, a mouse, a keyboard, a touch panel mounted on the display unit 350, or the like. The interface unit 340 is a data interface for inputting and outputting image data and control data. For example, the interface unit 340 is a wired communication interface such as USB, or a wireless communication interface such as a wireless LAN. The storage unit 320 stores data input from the interface unit 340. Alternatively, the storage unit 320 functions as a working memory of the processing unit 310. The physical quantity sensor 400 detects, for example, physical amounts such as an angular velocity and an acceleration, and outputs physical quantity data. The processing unit 310 performs a control process of various units in the electronic device and various data processes, based on the physical quantity data from the physical quantity sensor 400.

FIG. 21 is a diagram schematically illustrating a vehicle 206 as a specific example of the vehicle. A gyro sensor 204 (a physical quantity sensor) is incorporated into the vehicle 206. The gyro sensor 204 can detect the attitude of a vehicle body 207. The detection signal of the gyro sensor 204 is supplied to the vehicle body attitude control device 208. The vehicle body attitude control device 208 can control, for example, the hardness of the suspension and control the brakes of the individual wheels 209 according to the attitude of the vehicle body 207. In addition, such attitude control can be used in various vehicles such as a bipedal walking robot, an aircraft, or a helicopter. The gyro sensor 204 can be incorporated to realize attitude control.

Although the above embodiments are described in detail, it will be easily understood by those skilled in the art that many modifications can be made without practically departing from the novel matters and effects of the invention. Accordingly, all such modifications are included in the scope of the invention. For example, in the description or the drawings, the terms described together with the different terms which are broader or synonymous at least once can be replaced with the different terms anywhere in the description or the drawings. Further, all combinations of the embodiments and the modifications are included in the scope of the invention. The configurations and operations of the comparator, the circuit device, the physical quantity sensor, the electronic device, and the vehicle are not limited to those described in the embodiments, and various modifications can be made.

The entire disclosure of Japanese Patent Application No. 2016-145093 filed Jul. 25, 2016 is expressly incorporated by reference. 

What is claimed is:
 1. A comparator comprising: a first voltage-time conversion circuit which includes a first delay circuit, the first delay circuit being configured to receive a first input signal and a second input signal; a second voltage-time conversion circuit which includes a second delay circuit, the second delay circuit being configured to receive the first input signal and the second input signal; and a determination circuit communicating with the first and second voltage-time conversion circuits, the determination circuit being configured to determine a magnitude relation of the first input signal and the second input signal based on an output signal of the first voltage-time conversion circuit and an output signal of the second voltage-time conversion circuit, wherein the first delay circuit includes a first delay unit, the first delay unit including: a first falling edge delay circuit configured to delay a falling edge of an input signal received by the first delay unit based on the first input signal; a first rising edge delay circuit configured to delay a rising edge of the input signal received by the first delay unit based on the second input signal; and a first output circuit configured to separately receive an output signal from the first falling edge delay circuit and an output signal from the first rising edge delay circuit and generate a first delayed output signal based on the output signal from the first falling edge delay circuit and the output signal from the first rising edge delay circuit, and wherein the second delay circuit includes a second delay unit, the second delay circuit including: a second falling edge delay circuit configured to delay a falling edge of an input signal received by the second delay unit based on the second input signal; a second rising edge delay circuit configured to delay a rising edge of the input signal received by the second delay unit based on the first input signal; and a second output circuit configured to separately receive an output signal from the second falling edge delay circuit and an output signal from the second rising edge delay circuit and generate a second delayed output signal based on the output signal from the second falling edge delay circuit and the output signal from the second rising edge delay circuit.
 2. The comparator according to claim 1, wherein the first falling edge delay circuit includes: a first delay buffer receiving the input signal received by the first delay unit; and a first primary conductivity type transistor provided between a node of a first power-supply voltage and the first delay buffer, a current of the first primary conductivity type transistor being controlled based on the first input signal, wherein the first rising edge delay circuit includes: a second delay buffer receiving the input signal received by the first delay unit; and a first secondary conductivity type transistor provided between a node of a second power-supply voltage and the second delay buffer, a current of the first secondary conductivity type transistor being controlled based on the second input signal, wherein the second falling edge delay circuit includes: a third delay buffer receiving the input signal received by the second delay unit; and a second primary conductivity type transistor provided between the node of the first power-supply voltage and the third delay buffer, a current of the second primary conductivity type transistor being controlled based on the second input signal, and wherein the second rising edge delay circuit includes: a fourth delay buffer receiving the input signal received by the second delay unit; and a second secondary conductivity type transistor provided between the node of the second power-supply voltage and the fourth delay buffer, a current of the second secondary conductivity type transistor being controlled based on the first input signal.
 3. The comparator according to claim 2, wherein the first output circuit includes: a third secondary conductivity type transistor provided between an output node of the first delay unit and the node of the second power-supply voltage, the third secondary conductivity type transistor having a gate to which an output signal of the first delay buffer is input; and a third primary conductivity type transistor provided between the node of the first power-supply voltage and the output node of the first delay unit, the third primary conductivity type transistor having a gate to which an output signal of the second delay buffer is input, and wherein the second output circuit includes: a fourth secondary conductivity type transistor provided between an output node of the second delay unit and the node of the second power-supply voltage, the fourth secondary conductivity type transistor having a gate to which an output signal of the third delay buffer is input; and a fourth primary conductivity type transistor provided between the node of the first power-supply voltage and the output node of the second delay unit, the fourth primary conductivity type transistor having a gate to which an output signal of the fourth delay buffer is input.
 4. The comparator according to claim 2, wherein a delay time of the first delay buffer is controlled based on a current flowing through the first primary conductivity type transistor, wherein a delay time of the second delay buffer is controlled based on a current flowing through the first secondary conductivity type transistor, wherein a delay time of the third delay buffer is controlled based on a current flowing through the second primary conductivity type transistor, and wherein a delay time of the fourth delay buffer is controlled based on a current flowing through the second secondary conductivity type transistor.
 5. The comparator according to claim 1, wherein the first delay circuit includes a plurality of the first delay units connected in series; and the second delay circuit includes a plurality of the second delay units connected in series.
 6. The comparator according to claim 1, wherein the first voltage-time conversion circuit further includes: a first input signal generation circuit configured to generate the input signal received by the first delay unit; and a first latch circuit configured to operate based on an output signal from the first delay circuit, and wherein the second voltage-time conversion circuit further includes: a second input signal generation circuit configured to generate the input signal received by the second delay unit; and a second latch circuit configured to operate based on an output signal from the second delay circuit.
 7. The comparator according to claim 6, wherein the first input signal generation circuit is configured to change the input signal input to the first delay unit from a first logic level to a second logic level, and to change the input signal input to the first delay unit from the second logic level to the first logic level, in a case where the output signal of the first delay circuit changes from the first logic level to the second logic level, wherein the first latch circuit is configured to change the output signal of the first voltage-time conversion circuit from the second logic level to the first logic level, in a case where the output signal of the first delay circuit changes from the second logic level to the first logic level, wherein the second input signal generation circuit is configured to change the input signal input to the second delay unit from the first logic level to the second logic level, and to change the input signal input to the second delay unit from the second logic level to the first logic level, in a case where the output signal of the second delay circuit changes from the first logic level to the second logic level, and wherein the second latch circuit is configured to change the output signal of the second voltage-time conversion circuit from the second logic level to the first logic level, in a case where the output signal of the second delay circuit changes from the second logic level to the first logic level.
 8. The comparator according to claim 1, wherein the first voltage-time conversion circuit further includes a first measurement circuit that measures a number of pulses of an output signal from the first delay circuit, wherein the output signal of the first voltage-time conversion circuit is generated based on a measurement result of the first measurement circuit, wherein the second voltage-time conversion circuit further includes a second measurement circuit that measures a number of pulses of an output signal from the second delay circuit, and wherein the output signal of the second voltage-time conversion circuit is generated based on a measurement result of the second measurement circuit.
 9. The comparator according to claim 8, wherein the first voltage-time conversion circuit further includes a first ring oscillator which includes the first delay circuit, and in which the output signal from the first delay circuit is fed back to the input signal received by the first delay unit, and wherein the second voltage-time conversion circuit further includes a second ring oscillator which includes the second delay circuit, and in which the output signal from the second delay circuit is fed back to the input signal received by the second delay unit.
 10. The comparator according to claim 9, wherein the first voltage-time conversion circuit further includes a third input signal generation circuit that receives an enable signal and a signal based on the output signal from the first delay circuit, and generates the input signal received by the first delay unit, and wherein the second voltage-time conversion circuit further includes a fourth input signal generation circuit that receives the enable signal and a signal based on the output signal of the second delay circuit, and generates the input signal received by the second delay unit.
 11. A circuit device comprising the comparator according to claim
 1. 12. A circuit device comprising the comparator according to claim
 2. 13. A circuit device comprising the comparator according to claim
 3. 14. A physical quantity sensor comprising the circuit device according to claim
 11. 15. A physical quantity sensor comprising the circuit device according to claim
 12. 16. A physical quantity sensor comprising the circuit device according to claim
 13. 17. An electronic device comprising the circuit device according to claim
 11. 18. An electronic device comprising the circuit device according to claim
 12. 19. A vehicle comprising the circuit device according to claim
 11. 20. A vehicle comprising the circuit device according to claim
 12. 